A lithographic apparatus is a machine that applies a desired pattern onto a target portion of a substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that circumstance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising part of, one or several dies) on a substrate (e.g. a silicon wafer) that has a layer of radiation-sensitive material (resist). In general, a single substrate will contain a network of adjacent target portions that are successively exposed. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through the projection beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction.
The concept of a mask is well known in lithography, and it includes mask types such as binary, alternating phase shift, and attenuated phase shift, as well as various hybrid mask types. Placement of such a mask in the radiation beam causes selective transmission (in the case of a transmissive mask) or reflection (in the case of a reflective mask) of the radiation impinging on the mask, according to the pattern on the mask. In the case of a mask, the support structure will generally be a mask table, which ensures that the mask can be held at a desired position in the incoming radiation beam, and that it can be moved relative to the beam if so desired.
Another example of a patterning device is a programmable mirror array. One example of such an array is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that, for example, addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind. In this manner, the beam becomes patterned according to the addressing pattern of the matrix addressable surface.
In current apparatus, employing patterning by a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion at once. Such an apparatus is commonly referred to as a stepper. In an alternative apparatus, commonly referred to as a step and scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as here described can be seen, for example, from U.S. Pat. No. 6,046,792.
In a known manufacturing process using a lithographic projection apparatus, a pattern (e.g. in a mask) is imaged onto a substrate that is at least partially covered by a layer of radiation sensitive material (resist). Prior to this imaging, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement and/or inspection of the imaged features. This array of procedures may be used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemical, mechanical polishing, etc., all intended to finish off an individual layer.
If several layers are required, then it may be necessary to repeat the whole procedure, or a variant or portion thereof, for each new layer, with the overlay (juxtaposition) of the various stacked layers being performed as accurately as possible. For such purpose, a small reference mark is provided typically at one or more positions on the substrate, thus defining the origin of a coordinate system on the substrate. Using, for example, optical and electronic devices in combination with the substrate holder positioning device (referred to hereinafter as “alignment system”), this mark can then be relocated each time a new layer has to be juxtaposed on an existing layer, and can be used as an alignment reference. Eventually, an array of devices may be present on the substrate (wafer). These devices may then separated from one another by a technique such as dicing or sawing, whence individual devices may be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing,” Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4.
In designing a device such as an integrated circuit (IC), the basic elements for circuit design called cells are combined to form the device. In a logic circuit, for example, the cells are in inverter, an AND gate, a NAND gate, an OR gate, a NOR gate, an EXOR gate, an EXNOR gate, a flip-flop and a selector or multiplexer. In an analog circuit, for example, the cells are an amplifier, a comparator, an analog-to-digital converter (A/D converter), a digital-to-analog converter (D/A converter). In a memory circuit, for example, the cells are a memory cell such as an elementary memory RS flip-flop, a sense amplifier and a decoder. In a central processing unit (CPU) core circuit or a microprocessing unit (MPU), for example, the cells are a register, input-output (I/O) blocks and an arithmetic logic unit (ALU). However, cells may also be defined as higher level cells which can be made of blocks of elementary cells such as, for example, inverters, AND, NAND, NOR gates, etc. For example, cells can be defined as being CPUs, MPUs, or memories which, as discussed above, are a combination of elementary cells. Cells can even be defined as constituting large portions of a device, such as an integrated circuit.
FIG. 4 is a flow chart showing the various steps of a conventional method 400 for fabricating a device, such as an IC. The cells are designed by taking into account design rules restraints, strategy, device performance and the exposure system. The cells are stored in a cell library 410. To design a desired device 412, selected cells are retrieved from the cell library and a wiring is laid between the selected cells to form a data layout 414. The cell library is used repeatedly for designing several types of data layout. A same cell may be used for various device data layouts.
One or more computer programs are used to create a data layout of individual devices, i.e., cells, coupled together to perform a certain function. In order to fabricate the device, the circuit is typically translated into a physical representation, or layout. For example, computer aided design (CAD) tools can assist layout designers in the task of translating the discrete circuit elements or cells into configurations or shapes which will embody the devices themselves in the completed circuit. The result is a composite picture or “blueprint” of the circuit surface showing all the sublayer patterns. The shapes produce the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
To illustrate an example of a data layout, a simplified “imaginary” data layout 414 is represented in FIG. 4 in which cell A (represented by a circle), cell B (represented by a square), cell C (represented by a triangle) are connected to each other and in which cell B is connected to another cell A. For example, this data layout can be for a graphic accelerator or a digital signal processor (DSP) which can use a memory, a MPU and I/O blocks.
Once the layout of the circuit has been created, the layout is transferred to a physical template in which a mask is generally created in the mask fabrication process 416 for each layer of the circuit design. In this way, a set of masks 418 are created from the circuit data layout 414. Each mask created for each layer of the circuit design may comprise a plurality of different cells of the library of cells. The layers of a circuit represent the various fabrication steps or levels that are sequenced to form three dimensional regions (semiconductors regions) and interconnects (metal lines) that form the device circuit. For example, as illustrated in FIG. 1, the set of masks 418 comprises four masks (M1, M2, M3 and M4). Each mask (M1, M2, M3 and M4) corresponds to an individual layer of the circuit design.
The transfer of the layout to a physical template is performed by inputting the data representing the layout design 414 for that layer into a device such as an electron beam machine which writes the circuit layout pattern into the corresponding mask material. In less complicated and dense circuits, each mask comprises the geometric shapes which represent the desired circuit pattern for its corresponding layer. In more complicated and dense circuits in which the size of the circuit features approach the optical limits of the lithography process, the masks may also comprise optical proximity correction features, such as serifs, hammerheads, bias and assist bars, which are sub-lithographic sized features designed to compensate for proximity effects. In other advanced circuit designs, phase shifting masks may be used to circumvent certain basic optical limitations of the process by enhancing the contrast of the optical lithography process.
As circuit designs become more complicated, it becomes increasingly important that the masks used in photolithography are accurate representations of the original design layout. However, due to inaccuracies, design errors and compromises during the creation of the layout and the fabrication of the masks, the circuit fabricated according to the layout may not reflect the properties of the circuit designed. In the case of sub-micron ICs, designers increasingly rely on electronic design automation (EDA) tools to assist them in designing ICs and to make the necessary corrections to the various geometries of an IC mask layout to achieve the desired sub-micron IC images as the critical dimension (CD) becomes smaller. In order to ensure that the fabricated circuit functions according to the circuit design, the data layout is subjected to verification by testing each mask after fabrication with a mask testing procedure 420. For example, if a specific mask corresponding to a specific layer of the design is found to have errors, the mask is sent back to mask fabrication 416 where appropriate corrections to the mask can be implemented.
Even though the cells in the cell library 410 may be verified and tested, the layout design 414 once transferred into a physical representation in a form of set of masks 418 may include inaccuracies or errors because the steps following the creation of the layout design 414 on a computer, such as during the fabrication of the masks M1, M2, M3 and M4, are all unique. In addition, even though the same verified and tested cells from the cell library are used numerous times to create a design layout (for example cell A in the layout 414 is used twice), errors may still be present once the masks are fabricated. As a result, repeated verification of the same cell structures or blocks of patterns in the layout design may be necessary to ensure that the fabricated circuit functions according to the circuit design. This can be tedious and time consuming as each cell in each level of the layout design, i.e., in each mask M1, M2, M3 and M4, is verified and tested repeatedly. For example, cell A in each mask M1, M2, M3 and M4 corresponding to each level of the layout 414, should be verified twice because the cell A is used twice in the design layout 414.
The masks that are verified and found to be within production specifications are then used, for example, to optically project each mask M1, M2, M3 and M4 onto a substrate coated with a photoresist material in an exposure and projection process 422. For each layer of the design layout 414, radiation is used to project the features in the mask corresponding to that layer. As discussed above, the exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor substrate coated with a photoresist layer exhibiting a desired pattern which defines the geometries, features, lines and shapes of that layer. This process is repeated for each layer of the design. An array of devices is obtained on the substrate. These devices are then separated from one another by a technique such as dicing or sawing in the process of device fabrication 424. The individual devices can then be mounted on a carrier, connected to pins, etc.